1. Field of the Invention
The present invention relates to a data processor having registers greater in number than those which can be designated by a program instruction. More particularly, the present invention relates to an information processing apparatus which uses a plurality of register windows interchangeably.
2. Description of the Related Art
In order to improve the performance of a processor, it is necessary to speed up the operation of an arithmetic and logic unit of the processor and to improve the data transfer performance between the processor and a memory (main storage).
It is not always easy to improve the data transfer performance because of a data transfer delay caused by wirings and a limitation of the number of LSI pins connected to data transfer paths. Therefore, the data transfer performance becomes inferior to the arithmetic and logic operation performance. This bottleneck of the inferior data transfer performance hinders using the maximum performance of the arithmetic and logic unit. This problem is associated with not only microprocessors but also large computers. It becomes a serious problem particularly for large scale computations which processes a great amount of data.
Several attempts have been made to reduce the number of data transfers between a processor and a memory. Most of these attempts are directed to registers which store computation results and can be designated by an instruction. Typically, the following two conventional techniques are known.
The first conventional technique is called a register window technique. According to this technique, there are provided within a processor a plurality of registers (scalar registers) for storing data greater in number than those which can be designated by a register designation field of an instruction (scalar instruction). These registers equal to the number of registers which can be designated by a register designation field of a scalar instruction forms one group, and many of such groups are used interchangeably.
This first conventional technique is used by, for example, the SPARC architecture developed by Sun Microsystems, Inc., in U.S.A. For example, refer to J. L. Hennesy & D. A. Patterson, "Computer Architecture: A Quantitative Approach", pp. 450-451 (Morgan Kaufmann Publishers, Inc. (1990)).
With this technique, a plurality of scalar registers belonging to a register window currently used by a program are selected by register numbers designated by an instruction. As a result, a number of registers can be used greater than when register windows are not used.
With this technique, if the number of data storage registers provided within the processor is increased, the number of operations of saving an intermediate calculation result in the main storage and the number of operations of thereafter reading the intermediate calculation result from the main storage can be reduced, thereby reducing the number of data transfers between the memory and processor.
According to the second conventional technique, there are provided within a processor a plurality of vector registers capable of storing vector data comprised of a plurality of data, and vector registers in use are designated by an instruction. This conventional technique is used by many of today's super-computers. For example, refer to pp. 351-355 of the above-cited document.
With this conventional technique, each vector register stores vector data comprised of a plurality of data, and so an extremely large amount of data can be stored using a plurality of vector registers. The number of data transfers between the memory and processor can be reduced correspondingly. With the second conventional technique, it is possible to provide a plurality of additional scalar registers and selectively use these scalar registers designated by a scalar instruction, or to designate one scalar register and one vector register and perform a calculation using the scalar data in the scalar register and each of a plurality of vector element in the vector register.